Technical Field
The present invention relates to semiconductor devices and processes, and more particularly to semiconductor devices that employ doped ZnO for n+ layers to reduce defect-induced leakage.
Description of the Related Art
Metal oxide field effect transistors (MOSFETs), which employ III-V materials, such as GaAs, InP or InGaAs substrates, often include doped source and drain regions made of a similar material. In one common structure, III-V MOSFETs include source/drain (S/D) regions formed from doped InGaAs (e.g., n+ InGaAs). n+ InGaAs is not ideal for S/D regions. In InGaAs nFETs, the n+ InGaAs S/D regions suffer from a low doping concentration (e.g., 1×1019 cm−3). In addition, there is relatively high junction leakage and high contact resistance in InGaAs S/D regions. The junction leakage can be attributed at least in part to high dislocation density (e.g., about (e.g., greater than 1×109 cm−2) as a result of lattice mismatch between InGaAs and Si. In such instances, the dislocations become electrically active becoming a leakage source. To attempt to reduce dislocation density, a Ge buffer layer has been employed which reduces lattice mismatch from about 8% with Si to about 4% with Ge. However, dislocation density remains high (e.g., greater than 5×108 cm−2).